1. Field of the Invention
The invention pertains generally to inter-processor communication, and, more particularly, to inter-processor communication via mailboxes.
2. Related Art
A processor device in a multi-processor system architecture needs a capability of transferring information to the other processor devices in the system. Various inter-processor communication approaches have been used, with varying degrees of success.
One such approach utilizes a central memory for storing the information to be transferred. Each processor device has read-access and write-access to the central memory via a bus. Bus arbitration logic is used to allow each processor device read-access and write-access to the memory without bus collision or contention. Typically, the central memory is random access memory (RAM), used for storing the information which is passed between the processors.
Unfortunately, such approaches are costly, since they center around the combination of the central Ram to store the information and complex bus arbitration logic to provide each processor device both read-access and write-access to the Ram without bus collision or contention.
One example of the approach is Burkhardt, Jr., et al., "Intercomputer Communication Control Apparatus and Method", U.S. Pat. No. 5,142,683, which discloses a mailbox communication method and apparatus in which multiple processors have access to a common memory. A processor desiring to send a message to another processor inserts the message into its own mailbox, along with the address of the other processor. The sending processor interrupts the receiving processor, which, in response to the interrupt, scans the mailboxes to find the mailbox containing receiving processor's address and reads the message. Since the processors access common memory via a common work station bus, one disadvantage is that overhead is required to deal with bus contention and collision. Moreover, Burkhardt has another disadvantage, since communication paths may be tied up unless processors copy and clear mailbox information quickly.
An example of a shared common mailbox is found in Murray, Jr. et al,. "Data Multiplex Control Facility", U.S. Pat. No. 4,665,482, which discloses use of a mailbox between a CPU and an I/O microprocessor. Another example of a mailbox, which does not alleviate the disadvantages, is shown in Fiacconi, "Multiprocessor System with Interrupt and Verification Unit", U.S. Pat. No. 4,862,354.
Another approach that avoids bus collision or contention employs commonly available dual-port RAMs. Such RAMs incorporate RAM cells as well as 2-bus arbitration logic on a single chip, and allow both processor devices read-access and write-access to all RAM cells. In conventional dual-port RAM implementations, read information and write information is stored in the same RAM location. Thus, a way must be provided to prevent the write information from overwriting the read information. Using a dual-port RAM approach, when a sending processor device has information to be sent to a receiving processor, the sending processor device must first check to determine if the receiving processor device has written information to the RAM. If the receiving processor device has written information to theRAM, then the sending processor device must read the RAM before writing the information to be sent to the receiving processor device. The checking which is necessary in this approach unfortunately decreases the possible speed of the inter-processor communication.
This approach becomes increasingly costly and impractical as the number of processor devices in the system increases. For instance, with four processor devices in the system, a total of six dual-port RAMS would be needed to provide communication between each processor. As the number of processor devices in a system increases, the practicality and usefulness of this approach declines.